FIGS. 1A and 1B are schematic top views illustrating a partial layout of an integrated circuit chip, which mainly includes an active region 10 of a metal oxide semiconductor (MOS) element and gate structures 11, 12. According to the practical layout requirements, the gate structures 11, 12 may be arranged in two different directions, for example, as shown in FIGS. 1A and 1B, respectively. Portions of the active region 10 at opposite sides of the gate structures 11, 12 are source/drain regions, while a portion that is covered by the gate structures 11, 12 is a channel region. Thus, widths of the gate structures 11 and 12 define the length of the channel regions.
According to the design of an integrated circuit, a same chip may also include MOS elements of different channel lengths to provide different circuit characteristics such as on current (Ion). Also, the width of the gate structures 11 and 12 need to be changed according to the requirements. In addition, the circuit characteristic of MOS elements can also be modified by changing the implantation conditions for forming the source/drain regions.
However, as the size of MOS elements is becoming smaller and smaller, the widths W1, W2 of the gate structures 11, 12 reach to a resolution limit of a photolithography technique. Referring to FIG. 2, to reduce the critical dimension (CD) of gate structures, a dipole exposure technique, which employs a light source 20 of a shape differing from the conventional donut shape, is developed. The light source 20 would emphasis the exposure effect, in other words, exposure resolution, in a direction indicated by an arrow 22 (i.e., a direction parallel to the y-axis); however, the exposure effect in a direction indicated by an arrow 21 (i.e., a direction perpendicular to the y-axis) attenuates simultaneously. Thus, if the light source 20 is used to perform the exposure, the CD of the gate structure 11 in the direction parallel to the y-axis in FIG. 1A can be efficiently controlled, but the width W2 of the gate structure 12 in the direction perpendicular to the y-axis would be under an expected level due to the exposure attenuation. That is, the width W2 can't reach to a required dimension. At the same time, the width of the gate structure 12 is currently required having smaller CD. Therefore, the MOS element having a channel length of smaller CD, as shown in FIG. 1B, can't be fabricated using the light source 20 in FIG. 2. This limitation of the dipole exposure technique leads to reduced flexibility of product design. Thus, there is a desire to develop a new fabricating method that is capable of overcoming aforementioned disadvantages.